Changelog#

2026-08-31#

XDNA2 kernel: Replaced the fixed-size M64×K96×N64 BFP16 kernel, which suffered from a hardware hazard on the accumulator-register write port (DM_WM_L0_PORT) shared by VMOV and VLDA, with a parametrized one that receives m2, n2, and k1 in R0–R2 at runtime. At |m2|=|n2|=4 and |k1|=12, it issues 799 instructions, 768 of which contain a VMAC.F operation, and reaches 1761 BFP16 GFLOPS on a Ryzen AI Max PRO 390.
XDNA2 kernel design: Documented the accumulator-register write port. Added figures for register blocking, accumulation chains, and accumulator register buffering.
XDNA1 kernel: Corrected the instruction range of the loop body’s second half to lines 108–147.
Instruction set: Added more operations to the XDNA2 table, and the hardware-loop form of MOVXM to the XDNA1 table. Changed the XDNA2 vector store to VST <Xd> (previously WL/WH). Corrected the ISA tables based on the Peano (llvm-aie) machine model and assembler.
BFP16 format: Rewrote the description of bfp16ebs8: each entry of a block carries a signed 8-bit mantissa in two’s complement.
Minor changes: Assembly listings now color all six slots of a VLIW instruction. Further corrections to line references, terminology, and language throughout the website.

Initial version: The first release of the website contains an overview of the XDNA microarchitectures, instruction set tables for XDNA1 and XDNA2, and chapters on the data layout, design decisions, implementation, and efficiency of the XDNA1 and XDNA2 tensor contraction kernels. The repository includes the discussed sources: a BF16 M32×K32×N32 tensor kernel for XDNA1, a BFP16 M64×K96×N64 tensor kernel for XDNA2, and their microbenchmarks, including MLIR configurations and an XRT host driver.